Most integrated circuit (IC) devices today include a JTAG interface comprising TDI, TCK, TMS, TRST, and TDO bus signal terminals. The JTAG interface on the IC device is used for a myriad of purposes including but not limited too; testing purposes, debugging purposes, and programming purposes.
FIG. 1 illustrates a prior art arrangement of a serial string of IC devices 104 on a board 102. Each device 104 includes a JTAG interface comprising a control (C) bus of TCK, TMS, and optional TRST signals, an input (I) bus comprising a TDI signal, and an output (O) bus comprising a TDO signal. The control (C) bus (TCK, TMS, TRST), input (I) bus (TDI), and output (O) bus (TDO) are coupled to a JTAG test access port (TAP) 202 in the device as shown in FIG. 2. The TAP 202 is a well known access port defined in IEEE standard 1149.1 that operates to shift instruction and data patterns into and from the device 104 according to the state diagram of FIG. 4 and timing diagram of FIG. 5. In FIG. 5, the rising edge of the TCK signal times the operation of the TAP, the TMS signal controls the state diagram transitions of the TAP, the TDI signal inputs instruction or data patterns to the TAP, and the TDO signal outputs instruction or data patterns from the TAP. The JTAG interface of the devices 104 are connected in series such that the TAPs 202 of all devices 104 can be accessed at the same time from a JTAG controller 106, via the control (C) bus, input (I) bus, and output (O) bus.
FIG. 3 illustrates a prior art arrangement of boards 102 in a system 302. The boards typically exist in the backplane of the system 302. The boards 102 are connected in series such that the TAPs of all devices 104 on each board 102 can be accessed at the same time from a JTAG controller 106, via the control (C) bus, input (I) bus, and output (O) bus.
As can be seen in FIG. 3, serial arrangements of many boards 102 in a system backplane 302 can problematically extend the access time to the system due to the number of serial bits that must be shifted into and from each board 102 in the system 302 during each JTAG scan operation. Even more problematic, if a board 102 is removed from the system 302 the serial access connection to the JTAG controller 106 is disabled. In response to these system level JTAG scan access problems, JTAG Router devices were developed by National Semiconductor and Texas Instruments that allowed a JTAG controller 106 to directly address and access an individual board 102 in a system 302.
FIG. 6 illustrates the prior art concept of using a JTAG Router 604 to interface a JTAG controller 106 to one or more JTAG device strings 606 on a board 602. Each device string 606 may contain one or more devices 104. In operation, the JTAG controller 106 communicates to the JTAG Router 604 via bus 608 to address it and load selection control to it that selects one or more JTAG device strings 606 for access. The JTAG Router 604 can access one JTAG string 606 for access or it can serially concatenate and access multiple JTAG device strings 606 together for access. After the addressing and selection control input step, the JTAG controller 106 accesses the selected one or more JTAG device strings 606 via the JTAG Router and bus 608.
FIG. 6A is provided to indicate that a device string 606 may contain only one device 104. This will be the case for all device strings 606 shown in this disclosure.
FIG. 7 illustrates a prior art arrangement of boards 602 in a system 702. The boards 602 typically exist in the backplane of the system 702 so they can be easily removed for replacement or repair. The JTAG interface signals (I, C, O) of each board 602 are connected in parallel such that the each board is coupled to the control (C) bus 608 of the JTAG controller, the input (I) bus 608 of the JTAG controller, and the output (O) bus 608 of the JTAG controller. In this arrangement the JTAG controller can individually address and access any board 602 via the board's JTAG Router 604 and bus 608.
As can be seen in FIG. 7, the problematic scan access time mentioned in regard to serial JTAG access arrangement of FIG. 3 is eliminated since the JTAG controller 106 only performs scan operations to one board 602 at a time, via the board's JTAG Router 604. Also as seen in FIG. 7, the board removal problem mentioned in regard to FIG. 3 is eliminated since any remaining system boards 602 can be directly addressed and accessed by the JTAG controller 106, via the board's JTAG Router 604.
FIG. 8 illustrates a view of a prior art JTAG Router 802 produced by National Semiconductor and referred to as ScanBridge™. The ScanBridge 802 operates to address and select JTAG device strings 606 on boards 602 as described generally in the conceptual JTAG Router descriptions of FIGS. 6 and 7.
FIG. 9 illustrates the ScanBridge circuit 802 in more detail. The ScanBridge includes a Routing Circuit 902 and a JTAG TAP circuit 904. The JTAG TAP circuit 904 has a first set of TDI, TCK, TMS and TDO signals that are coupled to the JTAG controller bus 608, a second set of TDI, TCK, TMS, and TDO signals 910 that are coupled to the Routing Circuit 902, and control (CTL) outputs 912 that are coupled to the Routing Circuit 902. The JTAG TAP circuit 904 contains addressing circuitry that can be loaded by the JTAG controller 106 via bus 608 to address the board 602 and routing control circuitry that can be loaded by the JTAG controller via bus 608 to select one or more JTAG device strings 606 on the board for access. In response to the control (CTL) outputs 912 from the JTAG TAP circuit 904, the Routing Circuit 902 selectively couples the TDI, TCK, TMS, and TDO signals 910 from the JTAG TAP 904 to a selected TDI, TCK, TMS, and TDO signal group 906 that is coupled to a JTAG device string 606. The Routing Circuit 902 may also concatenate multiple JTAG device strings together and couple them to the TDI, TCK, TMS, and TDO signals 910 from the JTAG controller 904 in response to the control (CTL) outputs 912 so that they can be accessed together.
FIG. 10 illustrates the process of using JTAG scan operations 1002 to access a selected JTAG device string 606 on a board 602. Since the ScanBridge's JTAG TAP circuit 904 lies in series between the JTAG controller 106 and the selected JTAG device string 606, each JTAG scan operation 1002 to the selected JTAG device string 606 must be augmented with instruction and data patterns for the ScanBridge JTAG TAP circuit 904. Having to augment each JTAG scan operation 1002 with additional instruction and data patterns for the “in series” JTAG TAP circuit 904 is problematic since it lengthens the access time to the selected JTAG device string 606 and requires modifying the existing JTAG pattern set of the devices in the JTAG device string 606.
FIG. 11 illustrates a view of a prior art JTAG Router 1102 produced by Texas Instruments and referred to as a linking Addressable Scan Port (ASP). The ASP 1102 operates to address and select JTAG device scan strings 606 on boards 602 as described generally in the conceptual JTAG Router descriptions of FIGS. 6 and 7.
FIG. 12 illustrates the ASP circuit 1102 in more detail. The ASP includes a Routing Circuit 1202 and a Shadow Protocol Controller 1204. The Shadow Protocol Controller 1204 has a set of TDI, TCK, TMS and TDO signals that are coupled to the JTAG controller bus 608, and control (CTL) outputs 1206 that are coupled to the Routing Circuit 1202. The Shadow Protocol Controller 1204 contains addressing circuitry that can be loaded by the JTAG controller 106 via bus 608 to address the board 602 and routing control circuitry that can be loaded by the JTAG controller via bus 608 to select one or more JTAG device strings 606 on the board for access. In response to the control (CTL) outputs 1206 from the Shadow Protocol Controller 1204, the Routing Circuit 1202 selectively couples the TDI, TCK, TMS, and TDO signals 608 from the JTAG controller 106 to a selected TDI, TCK, TMS, and TDO signal group 906 that is coupled to a JTAG device string 606. The Routing Circuit 1202 may also concatenate multiple JTAG device strings together and couple them to the TDI, TCK, TMS, and TDO bus signals 608 from the JTAG controller 106 in response to the control (CTL) outputs 1206 so that they can be accessed together.
As seen, the Shadow Protocol Controller 1204 does not exist in series in bus 608 between the JTAG controller 106 and the Routing Circuit 1202, but is simply coupled to bus 608. The JTAG controller 106 communicates to the Shadow Protocol Controller 1204 using Shadow Protocol Messages to load board address and device string selection information during times when JTAG bus operations are inactive in the Run Test/Idle, Pause-DR and Pause-IR states of FIG. 4.
FIG. 13 illustrates the process of using Shadow Protocol Messages 1302 and 1304 to access a selected JTAG device string 606 on a board 602. When JTAG bus operations are inactive in one of the states mentioned above, the JTAG controller 106 inputs a Shadow Protocol Message request 1302 to the Shadow Protocol Controller 1204 that contains the board address and device string selection information. In response to the request 1302, the Shadow Protocol Controller 1204 outputs a Shadow Protocol Message acknowledge 1304 to the JTAG controller 106 to confirm the address and selection information, then connects the selected device string 606 to the JTAG controller 106 via bus 608. Following the connect operation, the JTAG controller 106 performs JTAG scan operations 1306 to access the selected device string 606. As can be seen, the JTAG scan operations 1306 only include instruction and data patterns required by the devices in the selected device string 606. Thus the ASP 1102 does not lengthen the access time to the selected JTAG device string 606 and does not require modifying the existing JTAG pattern set of the devices in the JTAG device string 606, as does the ScanBridge 802. However, the Shadow Protocol Messages 1302 and 1304 are based on Manchester-like encoding and decoding, which requires the Shadow Protocol Controller 1204 to be fairly complex which adds to the cost of the ASP device 1102.